Rayyan
Akbar

A custom digital design taken through the complete RTL-to-GDSII flow and fabricated on real silicon via the Tiny Tapeout program.

• Wrote synthesizable Verilog RTL and verified behavior in simulation before hardening.
• Ran the open-source OpenLane flow: synthesis, floorplanning, placement, CTS, routing, DRC/LVS signoff on the SkyWater SKY130 130 nm PDK.
• Worked within hard silicon constraints — fixed tile area, shared I/O mux, clocking rules — the same discipline as production tapeout checklists.

A hardware AI accelerator that classifies handwritten digits from the MNIST dataset — including digits drawn live with a PS/2 mouse — running entirely in programmable logic on a DE1-SoC.

• Implemented binarized neural network inference (XNOR → popcount datapath, 784→64→32→10 topology, weights trained quantization-aware) in Verilog-2001 for Quartus Prime.
• Verification-first workflow: built a bit-accurate Python golden model of the forward pass, then verified RTL simulation outputs against golden-model predictions across the test set — the reference-model methodology used in industry DV.
• Integrated a PS/2 mouse input path so users draw a digit on screen; an image decoder converts the canvas into a 784-bit input register and the result appears on the HEX display and VGA.
• Debugged a full-chip integration failure (layer I/O exceeding FPGA port limits) by rearchitecting Layers 1–3 to stream inputs/outputs through on-chip RAM.

A real-time game rendered from an FPGA where aiming is driven by a physical MPU-6050 accelerometer + gyroscope — a full sensor-to-pixels hardware pipeline.

• Wrote a Verilog I²C master to configure the MPU-6050 and stream 6-axis motion data.
• Processed raw accelerometer/gyro samples in hardware into stable aiming/motion control for gameplay.
• Drove VGA graphics and game logic entirely in RTL — sensor interfacing, data conditioning, and display in one clocked system.

An interactive game system on the DE1-SoC combining a Nios V soft processor with custom peripherals — the hardware/software co-design side of embedded systems.

• PS/2 mouse-driven control with pixel-accurate on-screen interaction.
• Double-buffered VGA rendering for tear-free animation, plus real-time audio streaming.
• Integrated processor, memory-mapped I/O, and display/audio subsystems into one working platform.

A quadrature receiver and mixer subsystem PCB for a software-defined radio — designed, hand-assembled, and validated on the bench with scripted measurements.

• Designed schematic and board layout in Altium Designer; hand-soldered and brought up the physical board.
• Wrote Python scripts to automate bench testing, driving repeatable measurement sweeps instead of manual point checks.
• Characterized the board with oscilloscope, waveform generator, and multimeter: measured 38 dB gain and I/Q quadrature phase match of 90° ±12.5°.
• Performed system-level validation with the full SDR chain to confirm the subsystem works in context, not just in isolation.

An LLM-based Python workflow that automates an entertainment news outlet's pipeline end-to-end, from content generation to publishing — and it isn't a demo: the platform was licensed to a media outlet and runs in production.

• Architected the full automation chain in Python: ingestion, LLM-driven drafting, and automated publishing — a hands-off pipeline where a failure at any stage is visible to a paying customer.
• Took it from personal project to a commercial licensing arrangement, owning reliability, iteration, and support for a real client.
• Same engineering muscle a DV team runs on: unattended multi-stage automation that has to work every time without a human watching it.